RTL Coding Styles That Yield Simulation and Synthesis Mismatches

New Verilog-2001 Techniques for Creating Parameterized Models

Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

 So decided to provide the link to this page. and it has got both free and commercial simulators documented.

http://en.wikipedia.org/wiki/List_of_Verilog_Simulators

October 13-15, 2008
Rhodes Island, Greece

http://vlsi.ee.duth.gr/vlsisoc-2008/

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CALL FOR PAPERS

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ABOUT VLSI-SoC 2008:

VLSI-SoC 2008 is the 16th in a series of international conferences sponsored by IFIP TC 10 Working Group 10.5 and IEEE CEDA that explores the state-of-the-art and the new developments in the field of Very Large Scale Integration Systems and their designs. Previous Conferences have taken place in Edinburgh, Trondheim, Tokyo, Vancouver, Munich, Grenoble, Gramado, Lisbon, Montpellier, Darmstadt, Perth, Nice and Atlanta. The purpose of the Conference is to provide a forum to exchange ideas and to show industrial and research results in the fields of VLSI/ULSI Systems, VLSI CAD and Microelectronic Design and Test.

Topics of interest include but are not limited to:

*Analog, Digital, and Mixed-Signal IC Design
*3-D Integration and Physical Design
*Deep Submicron Design and Modeling Issues
*New Devices and MEMS
*Testability and Design for Test
*CAD and Tools
*Digital Signal Processing and Image Processing IC Design
*Prototyping, Validation, and Verification
*Modeling and Simulation
*System-On-Chip Design
*Embedded Systems Design
*New Architectures and Compilers
*Reconfigurable Systems
*Low-Power Design
*Logic and High-Level Synthesis
* New Applications (communications, biosystems, video, automobile, security, sensor networks, etc.)
*Real-Time Systems

IMPORTANT DATES

SUBMISSION INSTRUCTIONS

Papers should present original research results not published or submitted for publication in other forums. Papers should not exceed 6 pages (single-spaced, 2 columns, 10pt font; see the VLSI-SoC website for detailed guidelines soon) and must be submitted electronically using the VLSI-SoC 2008 website. The proceedings will be published by IFIP (with ISBN) and available through IEEE Xplore. They will be distributed during the conference to all participants. A selection of the conference best papers will be invited to submit an extended version to be included as chapters of a book to be published by Springer.

GENERAL CHAIR
* Prof. Dimitrios Soudris, Democritus Univ. of Thrace, Greece

PROGRAM CO-CHAIRS
* Prof. Christian Piguet, CSEM, Switzerland
* Prof. Thanos Stouraitis, Univ. of Patras, Greece

PUBLICITY CO-CHAIRS
* Prof. David Atienza, Complutense U. of Madrid, Spain
* Prof. Bernard Courtois,TIMA Labs, France

KEYNOTE SPEAKERS
Prof. Eby Friedman, Univ. of Rochester, USA
Keynote Talk Title: “Interconnect-Based Design Challenges in High Performance Two- and Three-Dimensional Integrated Circuits and Systems”

Prof. Ahmed Jerraya, CEA/LETI, France
Keynote Talk Title: “Design and Programming strategies for MPSoC”

Dr. Roberto Zafalon, STMicrolectronics, Italy
Keynote Talk Title: “CLEAN: Leakage Aware Design for Next Generation’s SOCs”

STEERING COMMITTEE
* Manfred Glesner, TU Darmstadt, DE
* Ricardo Reis, UFRGS, BR
* Michel Robert, U. Montpellier, FR
* Luis Miguel Silveira, INESC ID, PT

CONFERENCE SECRETARIAT/WEB DESIGN
* Christos Baloukas
Democritus Univ. of Thrace
email: VLSI SOC 2008