Posts From EDA Tool Category

List of Verilog Simulators

We wanted to document list of Verilog Simulators and finally found that this list is already available in Wiki page.

 So decided to provide the link to this page. and it has got both free and commercial simulators documented.

http://en.wikipedia.org/wiki/List_of_Verilog_Simulators

What is EDApiX?

EDApiX is a Linux distribution based on Knoppix. The aim of the distribution is to provide a preconfigured and properly working environment with a set of open source, freely distributable tools for the electronic design. It is a live distribution and supports all the hardware and common free tools present in a linux distribution.

gEDA - GPL’d Electronic Design Automation

What is gEDA , its GPL‘d Electronic Design Automation.

The gEDA project has produced and continues working on a full GPL‘d suite of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout.

The gEDA project was started because of the lack of free EDA tools for UNIX. The tools are being developed mainly on GNU/Linux machines, but considerable effort is being made to make sure that gEDA runs on other UNIX variants.

Verilog Simulator from Pragmatic C Software

Pragmatic C develops and markets the commercial CVC Verilog compiler and also provides the Cver Verilog interpreter released as free software under the GNU GPL license.

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Icarus Verilog - Verilog Simulator and Synthesis Tool

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the “vvp” command. For synthesis, the compiler generates netlists in the desired format.

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