Pragmatic C develops and markets the commercial CVC Verilog compiler and also provides the Cver Verilog interpreter released as free software under the GNU GPL license.

CVER:

GPL Cver is a Verilog HDL simulator that is released under the GNU General Public License. GPL Cver is a full 1995 IEEE P1364 implementation with some Verilog 2001 features.

For more information on GPL Cver visit the GPL Cver page.

 CVC:

CVC is a native X86 Linux compiler and is many times faster than the Cver interpreter.

CVC simulation can be up to 20 times faster than interpreted Cver and is at least twice as fast for accurate delay gate level simulations. Procedural simulation is usually at least 5 times faster. Pragmatic is continuing to improve CVC simulation speed.