EDApiX is a Linux distribution based on Knoppix. The aim of the distribution is to provide a preconfigured and properly working environment with a set of open source, freely distributable tools for the electronic design. It is a live distribution and supports all the hardware and common free tools present in a linux distribution.

OpenCores - Home for Hundreds of IP cores.

FreeCores - Some of the Microprocessor cores and their links are captured in this website.

Would you like to learn FPGA Design from scrath, there is a blog , learning by doing is the idea behind this attempt.  Sven-Åke Andersson shares his success and setbacks through this blog at http://www.fpgafromscratch.com

What is gEDA , its GPL‘d Electronic Design Automation.

The gEDA project has produced and continues working on a full GPL‘d suite of Electronic Design Automation tools. These tools are used for electrical circuit design, schematic capture, simulation, prototyping, and production. Currently, the gEDA project offers a mature suite of free software applications for electronics design, including schematic capture, attribute management, bill of materials (BOM) generation, netlisting into over 20 netlist formats, analog and digital simulation, and printed circuit board (PCB) layout.

The gEDA project was started because of the lack of free EDA tools for UNIX. The tools are being developed mainly on GNU/Linux machines, but considerable effort is being made to make sure that gEDA runs on other UNIX variants.

Pragmatic C develops and markets the commercial CVC Verilog compiler and also provides the Cver Verilog interpreter released as free software under the GNU GPL license.

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Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the “vvp” command. For synthesis, the compiler generates netlists in the desired format.

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Design and Verification Conference & Exhibition is going to be on Feb 19-21, 2008

For more informations visit DVCon

IEEE version of the System Verilog is not available for Free download, but you can take the Accellera version of System Verilog LRM (version 3.1 Final) at the following link.

 http://www.eda.org/sv/SystemVerilog_3.1_final.pdf

Thanks to Open SystemC initiative, IEEE 1666™ Standard System C Language Reference Manual available at no charge in PDF format .

Visit IEEE PAge to download the same.

Dear Colleague,